Ultra-fast low-latent superconductor packet switching networks for petaflops computing

Abstract

This work is a part of a project to design a petaflops-scale computer using a hybrid technology multi-threaded architecture (HTMT). In the core of the superconductor part of the HTMT system there should be a high-bandwidth low-latency superconductor RSFQ switching network (CNET) connecting 4,096 computing modules with each other and with room-temperature semiconductor components. We present a study of the CNET for two alternative architectures: banyan and pruned high-dimensional meshes. The results indicate that with the speed and space limitations accepted in the HTMT concept, CNET will be able to provide a cross-sectional bandwidth of about 3/5 packet per processor per network clock cycle (in the HTMT concept, 32 ps). We have designed a simple 2/spl times/2 internal switching node which can be used to construct more complex networks using either of the architectures, and experimentally demonstrated successful operation of a 2-bit-wide data path.