Ultra-Compressed Three-Error-Correcting BCH Decoder

Abstract

3-Error-correcting BCH codes enable high-speed optical transport networks and low-latency next-generation memodes. The error locator polynomial root computation is the most hardware-demanding step in BCll decoding. For degree-3 polynomials, the roots can be found using a look-up table (LVT), which takes large area to implement when the code is not short. In this paper, a new method is proposed to further compress the LVT by more than an order of magnitude compared to the best prior design through utilizing the fact that only a limited number of degree-3 polynomials are valid error locators. A novel low-complexity approach is also developed to find the cube roots, which were not addressed in previous work, and the decoder architecture is further optimized. Compared to prior efforts, the proposed decoder achieves higher throughput and reduces the area requirement by 19% for a (1023, 993) BCH code over GF(210).