Ultra low-power sequential circuit implementation by a Quasi-Static Single phase Adiabatic Dynamic Logic (SPADL)

Abstract

This Implementation of sequential logic circuits by using a novel Quasi-Static Single-phase Adiabatic Dynamic Logic (SPADL) has been presented. SPADL uses only a single sinusoidal source as supply-clock. This not only ensures lower energy dissipation, but also simplifies the clock design which would be otherwise more complicated due to the signal synchronization requirement. Simplicity and static logic resembled characteristics of SPADL logic, substantially decreases circuit complexity with improved driving ability and circuit robustness. A practical adiabatic asynchronous sequential circuit based on the energy efficient SPADL is implemented with TSMC 0.18μm technology. Spice simulation shows that SPADL 8421 BCD code up counter circuits consume only 30% and 15% energy of single phase Clocked Adiabatic Logic(an existing single-phase based energy recovery logic), and static CMOS at100MHz. Both simulation and measurement results verify the functionality of such logic, making it suitable for implementing energy-aware and performance-efficient sequential circuit.