Ultra-low voltage start-up clock generators for micro-scale energy harvesting: New variants of body-biased stacked inverter based ring oscillators

Abstract

This work aims to discuss the challenges of implementing an integrated ultra low voltage start-up clock/oscillator, the state of the art and propose four new variants of a body-biased stacked inverter based ring oscillator and analyse the same. The proposed delay cells designed in 180-nm BCD CMOS process are connected to form a 13-staged ring oscillator (RO) with regular Vt transistors.All four proposed variants’ performance is compared against the former works (implemented in the same process) with respect to the lowest supply voltage required for sustained oscillations (VDDmin), oscillation frequency and peak-to-peak voltage swing (Vpp). For a supply voltage of 50 mV, over 90% VDD is obtained from post layout simulations for all four proposed architectures consuming around 24 pW of average power, out of which the variant that has the maximum swing of 92% (an improvement of 9.2% compared to that of stacked inverter based RO), is able to start and sustain an oscillation at 32.5 mV supply voltage. The fastest architecture proposed has a frequency (post layout) of 131.5 Hz at 50 mV VDD, which is 62% more than that of the stacked inverter based RO with body bias. Monte Carlo analysis reveals that the proposed RO variants’ Vpp have lesser interquartile range (IQR) and relatively higher median values.