Ultra Low Power III-V Tunnel Field-Effect Transistors

Abstract

Tunnel field-effect transistors (TFETs) have emerged as a potential device technology to replace conventional MOSFET technology in future ultra low power and high-speed nanoscale digital integrated circuits because of their extremely low voltage operation. Subthreshold slope (SS) of less than 60 mV/dec and very low leakage current are the main advantages of TFETs. However, TFETs suffer from poor ON current (ION) and ambipolar conduction. The poor ION and ambipolar conduction limit the RF performance of TFETs. This chapter highlights the performance of III-V materials-based TFETs for future ultra low power and high-speed applications. Bandgap engineering and gate metal work function engineering are two key design techniques that are widely used to improve the DC/RF performance of III-V TFETs. The use of hetero-gate dielectrics in III-V TFETs helps to reduce hot carrier effects (HCEs) and improves the reliability of TFETs at deep nanoscale regime compared to MOSFET technology. TFETs exhibit high immunity against short-channel effects (SCEs). Therefore, III-V TFETs with bandgap engineering, gate metal engineering, and gate dielectric engineering techniques are gaining enormous attention for next generation high-speed and ultra low power digital integrated circuit applications.