Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design

Abstract

To improve leakage power along with better cell stability, a 10 T SRAM cell is presented in this paper. Further, the proposed cell is used to implement a 6-input look up table (LUT) of FPGA and a 2 kb SRAM macroblock. The proposed cell achieves better results in terms of write static noise margin by 1.66 × , 1.8 × ; read static noise margin by 3.8 × , 1.37 × ; write trip point by 2 × , 2 × as compared to conventional (C) 6 T, read decoupled (RD) 8 T SRAM, respectively. The leakage power is also reduced to 0.07 × , and 0.43 × as compared C6T and RD8T SRAM, respectively at 0.3 V VDD.