Abstract
Ultra-high-frequency radio frequency identification reader receiver is implemented in 0.18 µm CMOS. Based on the key parameter analysis for the reader receiver, the dynamic range concept is proposed to define the specifications and evaluate the performance of a reader receiver. The presented receiver utilises a quadrature direct-conversion architecture which consists of passive mixers, baseband programmable gain amplifiers (PGAs) and low-pass filters (LPFs). Both good input matching and as high as 10 dBm input P1 dB of the RF front-end is achieved by utilising the passive mixers driven by square wave local oscillators. In the analogue baseband, four PGAs provide a gain control range higher than 80 dB and the LPFs have a reconfigurable bandwidth from 100 kHz to 1.6 MHz to optimise noise performance under different Rx data rates. The on-chip DC-blocker with controllable cut-off frequency is proposed to avoid DC offset problems and obtain a fast settling time simultaneously. In the normal mode, the receiver sensitivity achieves −74 dBm with 12.9 dB output signal-to-noise ratio. An alternative radio frequency receiving path with a low noise amplifier (LNA) improves the receiver sensitivity in the listen-before-talk mode by 14 dB. The total power dissipation is only 58 mW with 1.8 V supply voltage.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have