Ultra high density logic designs using transistor-level monolithic 3D integration

Abstract

Recent innovations in monolithic 3D technology enable much higher-density vertical connections than today's through-silicon-via (TSV)-based technology. In this paper, we investigate the benefits and challenges of monolithic 3D integration technology for ultra high-density logic designs. Based on our layout experiments, we compare important design metrics such as area, wirelength, timing, and power consumption of monolithic 3D designs with the traditional 2D designs. We also explore various interconnect options for monolithic 3D ICs that improve design density and quality. Depending on the interconnect settings of monolithic 3D ICs and the benchmark circuit characteristics, we observe that our two-tier monolithic 3D design provides up to 40% reduced footprint, 27.7% shorter wirelength, 39.7% faster operation, and 9.7% lower power consumption over the 2D counterpart.