Ultra compact pulse shrinking TDC on FPGA

Abstract

This study propose a new design of a field-programmable gate array (FPGA) based pulse shrinking time-to-digital converter (TDC), where only several configuration logic block (CLB) slices are required to achieve a resolution of around 2.38 ps. Taking advantage of the flip-flop’s asynchronous reset function, along with the characteristics of multiplexers, we propose an ultra compact design and a semi-automatic calibration method. Most importantly, a linear continuous response system for FPGA-based TDC implementation is suggested. Experiments using the Zynq Ultrascale + platform has demonstrated an on-chip resolution of 2.38 ps, DNL = [−0.23; 0.22], and INL = [−0.24; 0.27]. Further, we conducted and analyzed external measurements as well. The measurement range dropped from 210 ps to 80 ps as a result of precision degradation, while the resolution and non-linearity performance remain. This study will discuss the propagation delay, decoupling principle, the semi-auto calibration method, offset introduction, and temperature effects along with several delay tuning techniques.