Ultra Compact FDSOI Transistors including Strain and Orientation: Processing and Performance

Abstract

The different ways to boost the devices performance, by using local strain approach and crystalline orientations, are investigated. We focus on the CESL (Contact Etch Stop Layer) induced mechanical stress and on the specific technological features of FDSOI (Fully-Depleted). The impact of device geometry, buried oxide layer (BOX) and elevated source/drain is studied by using finite element mechanical simulations. The significant amount of stress transferred to the channel, observed by mechanical simulation, has been validated by systematic measurements. An important mobility improvement has been achieved for short gate length which is a mandatory condition for advanced CMOS low-power applications.