Ultimate solution for low thermal budget gate spacer and etch stopper to retard short channel effect in sub-90 nm devices

Abstract

For the first time, by employing low thermal budget processes of ALD SiO/sub 2/ and ALD SiN as gate spacer and silicide blocking layer, the short channel effects of CMOSFETs are significantly suppressed. Using the ALD SiO/sub 2/ and ALD SiN processes, we achieved excellent roll-off characteristics of threshold voltage in PMOS, which results in 10% increase of drive current and 15% decrease of inverter delay time. Furthermore, gate oxide reliability and static noise margin of 6T-SRAM bit cell with ALD SiC/sub 2/SiN processes are comparable to those with conventional high temperature CVD SiO/sub 2//SiN processes. In conclusion, ALD SiO/sub 2/ and ALD SiN processes of extremely low thermal budget are successfully implemented to sub-90 nm CMOSFETs.