Abstract

This paper introduces an integrated design and analysis CAD tool for SSO noise in PQFP leadframe packages. The CAD tool incorporates very efficient design and analysis algorithms which enable an accurate estimate of the maximum Simultaneous Switching Output Noise and the required numbers and placement of power and/or ground pins for pre-specified SSO noise limits in the initial design stage. Pre-specified package SSO noise is analyzed by using fast effective inductance reduction technique and SPICE simulation or analytic formulae.

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