Two-step pulse-shrinking time-to-digital converter

Abstract

This paper presents a two-step pulse-shrinking time-to-digital converter (TDC) consisting of a 4-stage coarse pulse-shrinking TDC with per-stage shrinkage 1ns and a 4-stage fine pulse-shrinking TDC with per-stage shrinkage 250ps. A simple residual time extraction scheme is proposed to extract the residual pulse of the coarse TDC. The characteristics of the TDC including mismatch and noise-induced timing errors, timing errors of delay blocks, conversion time, power consumption, and silicon consumption are analyzed in detail. The proposed TDC was implemented in an IBM 130nm 1.2V CMOS technology. Simulation results show that the proposed TDC offers 1.4ns conversion time, 1 LSB DNL and INL, and figure-of-merit (FoM) of 0.163pJ/step. Some measurement results of the proposed TDC are also presented.