Two-Step Inverse Modeling for Estimation of Channel Impurity Pile-up

Abstract

A scheme for estimating the amount of channel impurity pile-up using inverse modeling assuming a simplified effective impurity profile is proposed. Impurity profile is divided into deep and surface regions, and they are evaluated in two steps. In the first step, the impurity profile in the deep region is determined using the shift of threshold voltage, and then in the second step, the impurity profile in the surface region is determined using the threshold voltage. By taking drain-induced barrier lowering (DIBL) into account, this scheme can be used to estimate the effective impurity profile in short-channel devices, and thus, can be used to evaluate the gate length dependence of the channel impurity pile-up. Evaluated results on n-type metal–oxide–semiconductor field-effect transistors (MOSFETs) indicate that the impurity pile-up is strong and gate-length-dependent in spike-annealed MOSFETs, whereas laser-annealed MOSFETs show almost no impurity pile-up. The proposed scheme can be used to clearly detect such process condition dependence, and therefore, is helpful for process optimization.