Two-phase dynamic FET logic: an extremely low power, high speed logic family for GaAs VLSI

Abstract

A GaAs logic family that provides extremely low power dissipation, high density, and the full spectrum of logic circuit possibilities is described. It is implemented with a standard e/d MESFET foundry process. Two-phase dynamic FET logic (TDFL) is shown to operate up to 1 GHz with an extremely low power dissipation of approximately 30 nW/MHz-gate. It is self latching, lending itself to highly efficient implementations of pipelined systems. Finally, it is directly compatible with static DCFL (direct coupled FET logic) making its introduction into high speed systems very straightforward. >