Two-level Pipeline Scheduling of Adiabatic Logic

Abstract

We present an integer linear programming (ILP) formulation and a heuristic scheduling approach for high-level synthesis to synthesize two-level pipeline datapaths using four-phase adiabatic logic. Adiabatic CMOS logic that relies on charge recovery is attractive to achieve low energy dissipation. It complements voltage-scaling approaches, while its inherent pipeline structure makes it most suitable for signal processing applications. However, the differences between adiabatic and static logic, such as the phase clock controlled evaluation of each logic stage influences the automated design tools, making existing scheduling algorithms unsuitable for adiabatic circuits. We also present a VHDL description technique to perform functional simulation of the synthesized adiabatic datapath together with the static part of a digital system, and provide experiments to show the viability of our approach.