Abstract
Through-silicon vias (TSVs) are used as high-speed interconnects between dies in a 3D System-on-Chip (SoC). However, their speed cannot be utilized during test application due to inherent limitations of the scan chains of the cores, which prevent the use of high shift frequencies. Moreover, due to their high area cost, only a limited number of TSVs can be used for test application. As a result, the time needed for transferring test data to the cores in multiple dies can be considerable. We propose an efficient test-access mechanism (TAM) architecture, which exploits the high speed of TSVs to minimize the time for testing 3D SoCs. By the means of time-division multiplexing and an effective test scheduling method, the proposed TAM architecture offers significant savings in test time, TSV count and TAM cost.
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