Abstract
A novel layout approach of array cell (AC) architecture is described, which is dedicated to nMOS 4-phase dynamic logic. An AC is constructed of (M/spl times/N)+2 nMOSFETs which constitute each type of nMOS 4-phase logic gates. A graph theoretic approach to the nMOSFET placement in conjunction with a simulated annealing procedure is exploited for the area reduction in the layout design of the AC. A number of experimental results demonstrate the practicability of the proposed approach.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.