Abstract
In this paper, for the first time, a two-dimensional (2D) analytical sub-threshold model for sub-50 nm multi-layered gate dielectric recessed channel (MLaG-RC) MOSFET is presented and investigated using an ATLAS-2D device simulator, to counteract the large gate leakages and increased standby power consumption that arise due to continued scaling of SiO2-based gate dielectrics. The 2D model has been developed using a cubic polynomial potential distribution approach and includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain-induced barrier lowering (DIBL), sub-threshold drain current and sub-threshold swing using the minimum surface potential. A good agreement between the model predictions and device simulation results is obtained, verifying the accuracy of the proposed analytical model.
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