Two-dimensional analytical model for drain induced barrier lowering (DIBL) in short channel MOSFETs

Abstract

An analytical model to elucidate various effects of drain induced barrier lowering in a short channel MOSFET's performance is presented. In particular, the amount of drain bias induced depletion charge under the gate is assessed and an expression for the distribution of this charge along the channel length is developed. Then, based on a simplified two-dimensional solution of Poisson's equation along the channel, the potential barrier lowering between source and channel, and consequently threshold voltage shift is estimated. The results are compared with numerical simulation data for deep submicron NMOS devices. Finally, the dependence of threshold voltage on drain bias for LDD and non-LDD MOSFETs with effective channel lengths down to deep submicron range has been investigated. Due to its simplicity, the developed model is suitable for circuit simulators.