Two Stages Parallel LMS Structure: A Pipelined Hardware Architecture

Abstract

Modern wireless communication systems have tighten the requirements of adaptive beamformers when implemented on Field Programmable Gate Array (FPGA). The set requirements imposed additional constraints such as designing a high throughput, low complexity system with fast convergence and low steady state error. Recently, a parallel multi-stage least mean square (pLMS) structure is proposed to mitigate the listed constraints. pLMS is a two stages least mean square (LMS) operating in parallel and connected by an error feedback. To form the total pLMS error, the second LMS stage (LMS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) error is delayed by one sample and fed-back to combine with that of the first LMS stage (LMS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ). pLMS provides accelerated convergence while maintaining minimal steady state error and a computational complexity of order O(N), where N represent the number of antenna elements. However, pipelining the pLMS structure is still difficult due to the LMS coefficient update loop. Thus, in this paper, we propose the application of the delay and sum relaxed look ahead technique to design a high throughput pipelined hardware architecture for the pLMS. Hence, the delayed pLMS (DpLMS) is obtained. Simulation and synthesis result, highlight the superior performance of the DpLMS in presenting a high throughput architecture while preserving accelerated convergence, low steady state error and low computational complexity. DpLMS operates at a maximum frequency of 208.33 MHz and is obtained at the cost of a marginal increase in resource requirements, i.e. additional delay registers compared to the original pLMS design.