Abstract
Because of the great improvements in computer engineering, digital signal processing has been getting more and more important in recent years. Since discrete transformations play a significant role in digital signal processing, they have found many applications in various fields. The discrete cosine transform (DCT) is well known for its usefulness in the fields of image processing and data compression. With recent advances in the ISDN, limited communication bandwidth has become a new bottleneck, a possible solution to which may be an efficient encoding algorithm/architecture. The paper presents a two-stage algorithm and its corresponding architectures for efficient computation of a power-of-two length DCT. In this approach, the transform matrix of the DCT is decomposed into the product of two matrices, the preprocessing and the postprocessing ones. The elements in the preprocessing stage consist of 1, −1, and 0 only; the postprocessing stage is of block diagonal form in which each block performs a circular-convolution-like (CCL) operation. Thus, both stages can be implemented efficiently either by software or hardware. Details of the matrix decomposition are described and several corresponding architectures are also presented.
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