Two-Phase Read Strategy for Low Energy Variation-Tolerant STT-RAM

Abstract

An adaptive two-phase read strategy is proposed that allows reliable reads under high variability at a substantially lower energy, utilizing the idea of the conditional use of energy-costly variation-tolerance read. The proposed variation-tolerant design technique is developed for dealing with spatial variability while maintaining low read energy by using the conventional read with two-levels of reference voltages and the variation-tolerance read if a bit is not read out correctly by the conventional read. To achieve a two-phase read strategy, a sense amplifier (SA) is designed that performs both the energy-saving conventional read and the energy-costly variation-tolerant read. The energy overhead is significantly reduced by decreasing the use of variation-tolerant read, and the area overhead is minimized by reusing the conventional SA for the variation-tolerant read. The proposed circuit is evaluated using a compact spin-transfer torque magnetic RAM model, targeting an implementation in a 10-nm technology node. Results indicate that the proposed design strategy reduces read energy by 28.6% compared to the best-known variation-tolerant design with 3.7% area overhead assuming that a 1-bit cell is 20 $F^{2}$ and the number of rows is 1024.