Two phase non-overlapping clock adiabatic differential cascode voltage switch logic (ADCVSL)

Abstract

Adiabatic digital circuits have the ability to recover energy once committed in computation and make it available for recycling. However, although asymptotically zero energy per computation can be achieved using adiabatic circuits, there are two general issues preventing adiabatic system implementations from outperforming conventional CMOS designs in terms of energy efficiency. First, resonant circuits that provide a clock shaped power supply required by adiabatic circuits and exhibit negligible internal dissipation, are difficult to achieve. The problem is aggravated by the fact that most proposed adiabatic circuit families require multiple-phase clocking. The second issue is related to the design of sequential adiabatic logic circuits which typically trap charge in their internal nodes making a relatively large fraction of delivered energy unavailable for recovery. Adiabatic differential cascode voltage switch logic (ADCVSL) addresses both these issues.