Two New Techniques Integrated for Energy-Efficient TLB Design

Abstract

The translation lookaside buffer (TLB) is an essential component used to speed up the virtual-to-physical address translation. Due to frequent lookup, however, the power consumption of the TLB is usually considerable. This paper presents an energy-efficient TLB design for the embedded processors. In our design, we first propose a real-time filter scheme to facilitate the block buffering to eliminate the redundant TLB accesses without comparator delay. By modifying the address registers to be sensitive to the contents variation, the proposed real-time filter can distinguish the redundant TLB access as soon as the virtual address is generated. The second technique is a banking-like design, which aims to reduce the energy consumption per TLB access in case of block buffer miss. To alleviate the performance penalty introduced by the conventional banking technique, we develop two adaptive variants of the banked TLB. Both variants can achieve the high energy efficiency as the banked TLB while maintaining the low miss ratio as the nonbanked TLB. The experimental results show that by filtering out all the redundant TLB accesses and then minimizing the energy consumption per access, without any performance penalty our design can effectively improve the Energy* Delay product of the TLB, especially for the data TLB with poor locality