Two-Mode Reed–Solomon Decoder Using A Simplified Step-by-Step Algorithm

Abstract

Reed–Solomon (RS) codes are a type of forward error correction (FEC) coding that is highly efficient at combating burst errors in received messages. This efficiency has led to its widespread application in error correction in the head tag, often in combination with other channel coders for the construction of robust FEC coding. This brief outlines the design and implementation of a two-mode RS decoder using a simplified step-by-step (SS) algorithm for (255, 239) and (204, 188) RS codes. Calculation of the syndrome determinant in the RS decoder is achieved through Gaussian elimination using a 1-D systolic array with hardware architecture of low complexity, ideally suited for the higher-dimensional matrices used in SS algorithms. The proposed two-mode RS decoder is easily modified with regard to the delay-line buffer size, the delta accumulation and summation module, and the control unit. A two-mode RS decoder with approximately 32 K gates was fabricated using 180-nm complementary metal–oxide–semiconductor technology. Evaluation results confirm that the proposed device consumes only 57 mW at 166 MHz.