Abstract
AbstractWe present a sample preparation technique for using transmission electron microscopy (TEM) to profile the dopant in a specified doped region of a very large scale integrated (VLSI) devices. This technique is based on preferential etching of the doped region in silicon. Because the rate at which silicon is etched depends on the dopant concentration, the dopant distribution can be inferred by observing the thickness fringe. Using two-beam approximation and information on the dependence of the etching rate on the concentration, we calculated the intensity of the transmitted electron beam and found that the results agreed well with the observed fringes. In addition, by using a focused ion beam (FIB), we could also observe the dopant distribution in a specified source region of a VLSI device.
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