Abstract
There are many factors that can reduce the yield on chips. But there are checks that can be made at the physical verification stage and before to make sure you can get more working silicon than the bare minimum back from the fab. Planarity, which is the difference in oxide heights for a given region on a design, is an important factor affecting wafer yield. In order to correct planarity, it is first necessary to identify where low-density regions occur. DRC (design rule check) tools can be used to scan the chip in smaller increments and stepped across the chip to look for potential problem areas. This paper discusses the issues of metal fill, metal slotting and antenna effects.
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