Abstract
In this paper, a turbo iterative receiver structure with chip equalization is proposed for the 3G high-speed downlink packet access (HSDPA) system. The receiver equalizes the channel prior to the despreading and then performs two successive soft-output decisions, achieved by a soft-input soft-output (SISO) multicode detector and a SISO turbo decoder, through an iterative process. At each iteration, extrinsic information is extracted from detection and decoding stages and is then used as a priori information in the next iteration, just as in turbo decoding. Computer simulations show that the turbo iterative receiver structure for interference suppression and decoding offers significant performance gain over the traditional noniterative receiver structure.
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