Tunnel DCIV diagnosis of ultrathin gate oxide metal-oxide-silicon transistors

Abstract

The dc tunnel current–voltage method (tunnel DCIV) is demonstrated in this paper as a potential diagnostic monitor for process parameter variations of future generations of metal-oxide-silicon transistors. An example is given of p-channel metal-oxide-silicon transistors fabricated by 100 nm technology with 12.5 Å gate oxide. Tunnel current pathways in the gate oxide are described. Two figures of merit from the tunnelling current are suggested as a possible in-line monitor to evaluate process parameters in the basewell region and in the gate-overlapped drain and source extension regions. A zeroth-order one-dimension model is given to demonstrate the sensitivity of these two figures of merit.