Tuning Source/Drain Extension Profile for Current Matching in Nanowire CMOS Logic

Abstract

We present a novel approach for matching the drive current of n-FET with p-FET in CMOS logic circuits through source-drain extension profile tuning. Our approach overcomes the current quantization issue in nanowire/FinFET devices. We show that, in comparison to conventionally used method, where the width of p- device is increased to match the drive of n-device, the proposed approach provides significant reduction in circuit area and power consumption. When compared to the high-performance CMOS inverter (current matched using device width), the proposed method shows 28% lower area and 38% saving in power in case of Si-nanowire CMOS inverter. Further, the technique is applicable to planar CMOS showing excellent gain.