Abstract
Cortical circuits in the brain have long been recognised for their information processing capabilities and have been studied both experimentally and theoretically via spiking neural networks. Neuromorphic engineers are primarily concerned with translating the computational capabilities of biological cortical circuits, using the Spiking Neural Network (SNN) paradigm, into in silico applications that can mimic the behaviour and capabilities of real biological circuits/systems. These capabilities include low power consumption, compactness, and relevant dynamics. In this paper, we propose a new accelerated-time circuit that has several advantages over its previous neuromorphic counterparts in terms of compactness, power consumption, and capability to mimic the outcomes of biological experiments. The presented circuit simulation results demonstrate that, in comparing the new circuit to previous published synaptic plasticity circuits, reduced silicon area and lower energy consumption for processing each spike is achieved. In addition, it can be tuned in order to closely mimic the outcomes of various spike timing- and rate-based synaptic plasticity experiments. The proposed circuit is also investigated and compared to other designs in terms of tolerance to mismatch and process variation. Monte Carlo simulation results show that the proposed design is much more stable than its previous counterparts in terms of vulnerability to transistor mismatch, which is a significant challenge in analog neuromorphic design. All these features make the proposed design an ideal circuit for use in large scale SNNs, which aim at implementing neuromorphic systems with an inherent capability that can adapt to a continuously changing environment, thus leading to systems with significant learning and computational abilities.
Highlights
Brain processes large amounts of data in real-time in the presence of noise, while consuming little power
We propose a new Very Large Scale Integration (VLSI) implementation of a malleable synaptic circuit that is capable of mimicking the outcomes of various synaptic plasticity experiments
We demonstrate that the new design has a compact structure and possesses low power consumption, which is required for VLSI implementations of large-scale spiking neural networks
Summary
Brain processes large amounts of data in real-time in the presence of noise, while consuming little power. The dynamical behaviour of biological neurons is best understood through biophysically detailed models, such as the Hodgkin-Huxley (HH) model [1], which given the correct parameters, can replicate various experimentally observed response properties. Using such models one can develop hypotheses about cortical circuit behaviour and any underlying computations taking place. The complexity of such biophysical models can be a prohibitive bottleneck when translation into silicon is desired. For this reason simpler models, such as the Integrate-and-Fire (IF) [2,3], have been adopted in simulating networks, even though they lack the dynamic realism of real cortical circuits
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