Tunable Delay Element for Low Power VLSI Circuit Design

Abstract

We proposed a low-power tunable delay element with several nice features. Initially, we develop this matched delay element for implementing self-timed datapath components. Surprisingly, we found this design is also suitable for many high performance applications with low power requirement after examining its circuit characteristics in more detail. Tunable and asymmetric characteristics are the two major concerns of this delay line circuit. Besides, the circuit itself also demonstrates valuable characteristics such as well adjustment to the operating temperature disparity on the delay and the technology variation-tolerant nature. In order to keep the low power intuition of utilizing asynchronous circuits, we spend a huge effort to cut down the overall power consumption. The proposed tunable delay element consumes less average power than a 4-stage minimum size inverter chain. A 4 ns and 8 ns delay implemented by our design needs only 26 muw and 30 muw respectively for the TSMC 0.35 mum technology. To the best of our knowledge, this is the lowest power consumption of the programmable delay element of the same kind so far