TSV-aware 3D test wrapper chain optimization

Abstract

Three-Dimensional (3D) System-on-chips (SoCs) provides a promising solution to continue Moore's law, but it also brings challenging problems, one of which is the 3D test wrapper chain optimization problem. Since the minimization of test time is always the primary goal in integrated circuit (IC) testing, the balance of the lengths of all the wrapper chains is still an important concern for 3D SoCs. However, for 3D SoCs, through-silicon-vias (TSVs) are needed to connect cross-layer wrapper elements to form wrapper chains. Thus, in addition to balance these wrapper chains, we also need to reduce the number of required TSV. Since previous work only uses a postprocessing approach to reduce the TSV count, it may not be applicable if a rigorous constraint on the TSV count is given. In this paper, we propose a TSV-aware approach to perform 3D test wrapper chain optimization. Our optimization goal is to minimize the test time under the given TSV number constraint. Experiments with ITC'02 benchmark circuits consistently show that our approach can achieve the near-minimum test time under the given TSV count constraints.