TSV Characteristics and Reliability: Impact of 3D Integration Processes on Device Reliability

Abstract

There are many challenges in 3D integration circuit (3D-IC) with through-Si via (TSV) and metal bumps to be solved before the volume manufacturing starts. The most serious concerns are implications of stress/strain and metal contamination on device reliabilities in 3D stacked chips. Influences of mechanical stress and strain are introduced in wafer thinning process for 3D integration. Cu TSVs and metal bumps introduce significant mechanical stress and strain into thinned Si wafer. Active region in the 3D-IC with a thinned Si wafer might be more easily affected by metal impurity contamination. Because an extrinsic gettering (EG) region for gettering metallic contaminants during IC process is eliminated by the wafer thinning process, Cu atoms diffuse from Cu TSV when the blocking property of the barrier layer in the TSV to Cu is not sufficient. These Cu atoms may diffuse into both dielectric and active region of Si substrate during the back-end process and cause the performance degradation and early breakdown of devices. In this chapter, the influences of mechanical stress/strain effects introduced by Si thinning and metal bump joining and Cu impurity contamination effect introduced from Cu TSV and grinded surface on device reliabilities in thinned IC chips are discussed. DRAM may be sensitively affected by various parameters introduced in a 3D integration process. The impacts of 3D integration processes on memory retention characteristics in thinned DRAM chip are introduced for reliable 3D DRAM.