TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM

Abstract

High-bandwidth memory (HBM) is the latest 3-D-stacked dynamic random access memory (DRAM) standard adopted in Joint Electron Device Engineering Council (JEDEC). It has many advantages, such as high bandwidth, large capacity, and low power consumption, but mass production is challenging due to its low yield and reliability. One of the reasons is that through-silicon-vias (TSVs) are prone to defects. Therefore, HBM requires a TSV built-in self-repair (TBISR) architecture that can repair the TSV at a high repair rate even after chip shipment; however, implementing it through existing TSV repair architectures is difficult. They have a large area overhead or a low repair rate. In addition, they lack consideration for bidirectional TSV repair. To address these issues, this article proposes a novel TBISR architecture that can repair bidirectional TSVs and has a small area overhead and a high repair rate. Experimental results show that the proposed architecture, capable of bidirectional TSV repair, has a high repair rate, despite the small size compared to other architectures.