Triplet Based Multi-core Interconnection Network and its Computational Efficiency

Abstract

Any communication model can be well characterized by locality properties and, any topology has its intrinsic, structural, locality characteristics. Spatial locality of processing cores in a multi-core chip can be exploited to gain computational efficiency of a network on chip. In this paper we propose a new criterion in performance evaluation of NoC architecture that is based on the concept of group locality in an interconnection network, the "lower layer complete connect". TriBA a new idea in multi-core architectures and a direct interconnection network (DIN), is compared with 2D mesh on single chip multi core architecture. TriBA consists of a 2D grid of small, programmable processing units, each physically connected to its three neighbors so that advantageous features of group locality can be fully and efficiently utilized for getting maximum out of an on-chip interconnection of cores. Cores on the same chip are connected via triplet-based hierarchical interconnection network (THIN), which has simple topology and computing locality characteristic. We have modeled execution of dense matrix and sorting algorithm on an on-chip multi core interconnection network. Our results show that triplet based interconnection architecture has strong spatial locality characteristics in comparison to the conventional 2D mesh. The computational efficiency of triplet based interconnection is remarkable when the number of processing cores increase substantially.