‘trimoda’ Wafer-Level Package: Fully Compatible Electrical, Optical, and Fluidic Chip I/O Interconnects

Abstract

We describe the fabrication, assembly, and testing of a wafer-level package with fully compatible electrical, optical, and fluidic ('trimodaP) chip I/O interconnects. Various trimodal interconnect configurations are introduced. The trimodal I/Os are fabricated using five minimally demanding masking steps. In order to experimentally characterize the trimodal I/Os, we fabricate two separate substrates to test the chips with these I/Os in a piecewise manner. In the first assembly demonstration, we perform electrical and optical I/O interconnection measurements. In the second assembly demonstration, we perform electrical and fluidic interconnection measurements. Measurements reveal that the metal-clad optical pins (55times110 mum in size) attenuate an optical signal (632.8 nm wavelength) by 3.6%. The electrical resistance is measured to be 50 mOmega. It is also shown that the fluidic I/Os with the integrated back-side thermofluidic microchannel heat sink can achieve thermal resistance as low as 0.17degC-cm2/W. Cooling of localized power density of >300 W/cm2 is also demonstrated. Mechanical testing of polymer pins before and after metallization is also reported.