Abstract
We propose a post-fabrication trimming method for the silicon-on-insulator photonic platform based on localised laser annealing of hydrogen silsesquioxane (HSQ) cladding. The technique is fast, does not degrade the device performance, does not require additional fabrication steps, and can therefore be implemented at minimal cost. Here we experimentally demonstrated how the spectrum of a ring resonator can be shifted by over 1 nm by annealing a section of the device as short as 30 µm, corresponding to a change in the effective refractive index of ∼10-2. Modifications of both the HSQ refractive index and its chemical structure as a function of the annealing temperature are also discussed. Trimming of multi-ring resonators indicate that this technique can be effectively used for post-fabrication reconfiguration of complex photonic circuits or to compensate for the fabrication tolerances of a typical CMOS process.
Highlights
In recent years, silicon on insulator (SOI) has established itself as the dominant platform for integrated photonic circuits [1]
We propose a post-fabrication trimming method for the silicon-on-insulator photonic platform based on localised laser annealing of hydrogen silsesquioxane (HSQ) cladding
By and large its prominence is based on compatibility with the CMOS process and a compact device footprint enabled by the high index contrast between the silicon core and buried oxide (BOX) layers
Summary
Silicon on insulator (SOI) has established itself as the dominant platform for integrated photonic circuits [1]. In resonators implemented using typical single mode quasi-TE waveguides the amount of shift is proportional to the variation in waveguide dimensions, such that a change in width of 1 nm translates to approximately 1 nm shift in the spectral response [5] This becomes critical in designs that make use of cascaded resonators where a decrease in Q-factor can be observed due to a mismatch in resonant wavelength of individual devices. Active tuning can be implemented by changing the refractive index of the core by either exploiting the thermos-optic coefficient using a thermal heater [6] or free-carrier dispersion using a pin junction [7] While effective, this approach suffers from increased power consumption, which can be unacceptable in certain applications such as optical interconnects, where the target power consumption is set in the order of pico-joules per bit [8]. The technique is best suited for use in cases where continuous reconfiguration of the circuit is required, as opposed to static correction for fabrication error
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