Tri-Dimensional A2-RAM Cell: Entering the Third Dimension

Abstract

Chapter we present an overview of a capacitor-less DRAM cell based on a 3D multibody transistor with high scalability, low-power consumption, long retention time, non-destructive reading, and wide memory window. High performance is demonstrated on a 20 nm channel length device, including ‘1’ to ‘0’ current ratio larger than 103 (with negligible ‘0’ current level), very low voltage bias operation and retention time longer than 20 ms at 85 °C in worst cases. Compared to previous equivalent 3D memory cells reported so far, the proposed cell shows longer retention time even though the gate length is shrunk by a factor of two. The voltages used to write and read the information are far smaller than the previously reported ones in comparable structures. We have confirmed by TCAD simulation that the improvements are attributed to an innovative operation concept: a dedicated body partitioning. This device exploits the working principle of the A2RAM memory cell recently introduced by researchers at the University of Granada and Grenoble INP. The principles of operation and key mechanisms for programming are described. The new concept of 3D (FinFET, trigate or nanowire) DRAM cell proposed features a N/P body partitioning which enables the physical separation of hole storage and sensing electron current. The hole concentration in a surrounding P-crust, controls the partial or full depletion of a N-core which short-circuits drain and source of the device. The status of the N-bridge (depleted or un-depleted) determines the two memory logic states. The cell is compatible with ultimate scaling and shows attractive performance (long retention, wide memory window, simple programming, nondestructive reading, and very low-power operation) for embedded systems.