Trench oxide protection for 10 kV 4H-SiC Trench MOSFETs

Abstract

This paper evaluates the use of trench oxide protection on ultra high voltage trench MOSFETs in 4H-SiC. The placement of a p/sup +/ implant under the trench of the MOSFET significantly reduces the peak of the electric field in the trench oxide, thus guarding against premature oxide rupture before reaching the targeted breakdown voltage. Due to this implant, the forward characteristics are severely distorted resulting in a specific on-resistance of 8.6 /spl Omega//spl middot/cm/sup 2/ for the protected UMOSFET compared to 310 m/spl Omega//spl middot/cm/sup 2/ obtained with its unprotected equivalent, for a current density of 50 A/cm/sup 2/. This distortion is due to the JFET effect that arises due to the p/sup +/ implant (and the large difference in doping concentrations of the implant and the voltage blocking layer). Quasisaturation effects in the forward characteristics have also been observed. In addition, for the voltage rating of 10 kV, the electric field in the oxide is much lower that its critical value, and that trench oxide protection is unnecessary for devices with this voltage rating. To guard against possible electric field buildup in the trench corner however, pronounced curvature in the trench corner has been incorporated into the trench MOSFET to improve its performance.