Trench Gate Nanosheet FET to Suppress Leakage Current From Substrate Parasitic Channel

Abstract

Recently, nanosheet FETs (NS FETs) have been introduced as promising candidates for beyond 3-nm node technology. However, difficulties remain for mass production of the NS FETs. One of the concerns is increased OFF-state current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{OFF}}$ </tex-math></inline-formula> ) due to leakage current from the substrate parasitic channel. Since the NS FET includes a 2-D parasitic FET on the bottom substrate, increased leakage current through the bottom is inevitable. The traditional methodology to suppress the leakage current from the parasitic channel is to use a punchthrough stopper (PTS). However, the PTS requires both ion implantation and an annealing process, which are detrimental to device yield. In this context, the trench gate (TG) NS FET is proposed as a new device architecture. The TG structure increases the effective gate length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{G\text {,EFF}}$ </tex-math></inline-formula> ) of the parasitic FET, reducing the leakage current through the bottom. Moreover, the fabrication process for the TG NS FET is fully compatible with conventional processes.