Abstract
The TRB3 features four FPGA-based TDCs with < 20 ps RMS time precision between two channels and 256+4+4 channels in total. One central FPGA provides flexible trigger functionality and GbE connectivity including powerful slow control. We present recent users' applications of this platform following the COME&KISS principle: successful test beamtimes at CERN (CBM), in Jülich and Mainz with an FPGA-based discriminator board (PaDiWa), a charge-to-width FEE board with high dynamic range, read-out of the n-XYTER ASIC and software for data unpacking and TDC calibration in ROOT. We conclude with an outlook on future developments.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
