Trapping mechanisms in negative bias temperature stressed p-MOSFETs

Abstract

Abstract Device parameter degradation of p-MOSFETs after N egative B ias T emperature Stress (NBTS) and the related charge trapping mechanisms are investigated in detail. Applying specific annealing experiments to NBT-stressed transistors, the influence of stress-induced oxide charge build-up and interface state generation on the degradation of the electrical parameters is evaluated. It is found, that hole trapping significantly contributes to the NBTS-induced Vt shift. Furthermore, experimental results of the hot-carrier behavior of virgin and NBT-stressed devices demonstrate that only weak correlations between these types of stress and the involved degradation mechanisms exist, which is important in applications with alternating stress situations.