Abstract
Recent attention has focused on trapezoidal reference-based pulse width modulation (PWM) schemes in multilevel converters (MLCs) with easier implementation and better harmonic performance. Nevertheless, these studies utilize trapezoidal reference only for multi carrier PWM methods and details of FPGA implementation are not provided. This paper proposes a trapezoidal reference-based single carrier PWM (TSC-PWM) with its novel FPGA implementation. Design parameters of TSC-PWM is determined such that harmonic performance is maximized and architectural details of FPGA implementation of TSC-PWM are provided. Results reveal that TSC-PWM significantly reduces the resource utilization compared to other methods. Single-phase three-module cascaded H-bridge MLC (CHB-MLC) is established in both simulation and experimental platforms. Results indicate that the TSC-PWM provides better harmonic performance along with higher DC utilization ratio compared to other methods. Moreover, both half-wave and quarter-wave symmetries are ensured with TSC-PWM.
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