Abstract
Through 3D TCAD simulations with single charge traps, we discovered a direct evidence to the mechanism of DRAM row hammer effect. It is governed by a charge pumping process, consisting of charge capture and emission under or around an aggressor wordline and subsequent carrier migration to a victim storage node. The process is highly sensitive to the location and energy level of acceptor-type traps; a single trap may enhance the row hammer effect by a factor of 60 in a 2y-nm node. Dependencies on bitline junction depth, temperature, and hammering waveform are analyzed, and the results are in good agreement with previously reported experiments. Feature size scaling is found to aggravate the row hammer effect.
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