Trap Charges in High-k and Stacked Dielectric

Abstract

The current scenario in the semiconductor device area is well known to us all. In the last couple of decades, the downscaling of devices mainly focuses on field and voltage scaling. But here our area of discussion will be on field scaling because this affects the physical dimension of the devices including the channel length, channel thickness, oxide thickness, etc. As the thickness of the dielectric plays a crucial role in the operation of the field effect transistors, the scaling of oxide thickness remains in the spotlight for researchers. To meet the present industry demand, the conventional dielectric used as gate oxide, i.e., silicon dioxide (SiO2), turns as a porous sheet, which results in unwanted gate leakage current. So researchers are going for the high-k dielectric material to resolve this issue. Again, to achieve more gate control over the channel and hence to minimize the majority of short channel effects (SCEs), researchers and industry professionals are turning to multi-gate devices. Unlike single-gate devices, multi-gate structure has to be designed with a higher number of oxide layers corresponding to each gate electrode. This results in a higher number of interface layers or, in other words, larger area of interface between the oxide and the semiconductor region. However, the trapping of charges in the oxide region or oxide semiconductor interface needs to be discussed in detail, with consideration of high-k, for further improvement of our devices. There are mainly two types of charge trapping involved that we need to discussed in oxide layer for FET application purpose: (i) interface trap charges (ITCs) and (ii) oxide charges (OC). If we try to distinguish between these two charges, the gate bias can be very informative for this, because the interface trap charges vary with the gate applied field whereas the oxide charges not. Oxide charge can be categorized predominantly in three types on the basis of their technological importance, namely interface charge sheet (Qf), oxide trapped charges (Qot), and mobile ionic charge (Qm). Here we need to know the significance of each type, so we shall start with their definition. Our first type of charge as mentioned above can be identified as the remaining charge density after the annealing procedure. This is usually located at or very close to the interface of dielectric and semiconductor. The Qot can be found at the gate metal and oxide interface, and also can spread over the entire oxide region. The third and last type, i.e., mobile ionic charge, is introduced to the dielectric only through the alkali metal gate electrode. Hence these are usually present at the metal and oxide interface at no gate bias and all over the dielectric region at the biasing stage. Analysis and optimization of unwanted charge cloud present over the high-k dielectric region in multi-gate devices are more important than in single-gate devices. If we consider designing a multi-gate structure, we need to introduce a higher number of dielectric layers with respect to the number of gates. Trap charges creation or presence in these layers influences the channel behavior such as inversion layer build-up, threshold voltage roll-off, gate leakage current, etc. Again, in memory-based design, these dielectric materials sometime have more relaxation current due to the defects created during the fabrication or operation. Fabrication of these layers is more complicated than the conventional SiO2, and hence choosing an appropriate material for specific application can be vital. The above-discussed traps can sometime outweigh gate control even in multi-gate devices, especially for low-power design. Now the primary focus of our discussion will be on how these charges affects the capacitance of MOS capacitor and FETs operation, and hence the selection of our high-k dielectric for future scaling of our multi-gate designs and their application.