TRANSPUTER IMPLEMENTATION FOR LOW-LEVEL IMAGE PROCESSING SYSTOLIC ARRAY DESIGNS

Abstract

This paper describes transputer implementation of systolic array designs of parallel algorithms for low-level digital image processing, in particular we consider the gradient operator. To achieve high performance, a new systolic array in which all the cells in a double pipeline are interconnected to a system bus. The transputer implementation of the design, is discussed. Comments and conclusions related to the implementation of the systolic array on transputer networks are provided in the performance section. It is then shown that the systolic array design can be extended to handle the Prewitt and Sobel operators and inverse gradient filter.