Abstract
A new translation look-aside buffer(TLB) design method with cache resource reusing was proposed for reducing the power consumption and area cost in the embedded processor.This method bases on a two-level TLB architecture and an address mapping table of cache,and decreases the frequency of TLB accesses with low power consumption.The dynamic expansion mechanism of TLB entry with cache resource reusing enlarges the mapping range of physical address for high TLB hit rate.Moreover,a locking method of TLB entry was proposed to balance the resource hazard between TLB entry and instruction/data in cache.Comparing with the traditional TLB design,experiments showed that the proposed method reduced the power consumption and the area cost of embedded processor by 28.11% and 21.58% respectively.
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