Translating VHDL into functional symbolic finite-state models

Abstract

In this paper we present a method to translate VHDL into symbolic finite-state models. Our method can handle those aspects of VHDL which have a finite representation obtaining the semantics defined in the IEEE statndard. We describe an intermediate representation based on finite automata and its translation into a BDD-based reperesentation. Our model interfaces VHDL with a BDD-based functional symbolic model checker.